1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a MOS transistor and fabricating method thereof. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for modifying a configuration of a gate electrode.
2. Discussion of the Related Art
Generally, in fabricating a semiconductor integrated circuit, one transistor is fabricated on a silicon die of 1-2 mm in the early stage of development. Lately, millions of unit devices are integrated on a 20 mm×20 mm silicon die. A size of a unit transistor needs to be reduced into a minimal size to enable such a fabrication of the integrated circuit. For this, many efforts are made to research and develop various fabricating processes.
To scale-down a unit transistor configuring an integrated circuit, a substrate of a very thin junction having a high degree of diffusion and a very large curvature in source-drain diffusion regions is needed. Thus, in the drain-substrate junction having a steep density slope of impurities, a problem of impact ionization attributed to hot carriers is induced. To solve this problem, the lightly doped drain (LDD) structure has been developed. The LDD structure is formed by defining a boundary of a polysilicon gate and forming an LDD extension line that settles an extension of channel using N-type impurities.
After a gate electrode and source-drain diffusion regions of a transistor have been formed, a contact with a metal line is formed to electrically connect them to an external device. A sheet resistance of the source-drain diffusion region fails in avoiding being reduced below 10-20 ohms/square. Forming the polysilicon gate to be thin according to the scale-down of the transistor also fails in avoiding being reduced below 10-20 ohms/square. Hence, usefulness as a mutual access medium is considerably decreased.
To solve this problem and to enhance the mutual access, a method of forming silicide having a low specific resistance on silicon of a gate or source-drain region has been developed. In particular, a process of forming silicide on both of the gate and the source-drain regions of the transistor is called salicidation. Salicidation is able to eliminate parasitic capacitance caused by the overlapping that may be generated between the source/drain and the gate. Salicidation is able to reduce contact resistance and source/drain internal resistance due to the increased contact area between metal and source/drain.
A method of fabricating a MOS transistor in a semiconductor device according to a related art is explained with reference to FIGS. 1A to 1E, as follows.
First, on an active area of a substrate 10 reserved for a transistor, a gate oxide 20 and a polysilicon 30 are sequentially stacked. They are then patterned by photolithography to remain on an area reserved for a gate electrode only. Hence, a structure shown in FIG. 1A is configured.
Referring to FIG. 1B, ion implantation is carried out with low-density impurities having a conductive type opposite to that of the substrate 10 using the polysilicon gate 30 formed in FIG. 1A as a mask. The substrate 10 is then annealed to form an LDD region 22a. 
After the LDD region 22a has been formed, an oxide layer is formed over the substrate 10 by low-pressure chemical vapor deposition. The oxide layer is then etched to remain on a sidewall of the gate 30 only. The oxide layer remaining on the sidewall of the gate 30 is a spacer 32 that serves to prevent a short-circuit between the gate and a source/drain diffusion region in salicidation The spacer 32 is shown in FIG. 1C.
Referring to FIG. 1D, impurity ion implantation and annealing are carried out using the polysilicon gate and spacer 30 and 32 as a mask to form heavily doped source/drain diffusion regions 22b. Subsequently, a metal such as Co, Ti, and the like is deposited over the substrate 10 to form salicide by reaction with silicon or polysilicon. Salicide layers are then formed on the polysilicon gate and the source/drain diffusion regions over the silicon substrate by sintering. Metal that does not react is selectively removed by etching. Thus, the self-aligned silicide is called salicide. The salicide layers 24a and 24b are formed on the polysilicon gate 30 and the source/drain diffusion regions, respectively.
However, the related art method of fabricating the semiconductor device has the following problems or disadvantages.
First, as the degree of integration of the circuit increases, the unit transistor devices are formed adjacent to each other. If so, as the gate electrodes of the transistors are provided too close to each other, a gap between the gates becomes narrower. Hence, an exposed area of the source/drain diffusion region between the gates having the oxide spacers 32 formed thereon respectively is reduced. That is, the area having the salicide formed thereon in the source/drain diffusion region, as shown in FIG. 2, is considerably reduced. Hence, a space margin for forming a contact in the source/drain diffusion region becomes short. The sheet resistance increases since it is difficult to form the salicide.
Secondly, the increased degree of integration of the circuit means the fine reduction of a width of the gate electrode. Therefore, the salicide formed on the narrow gate electrode is provided with an insufficient area. Hence, limitation is put on the formation of a low-resistance line on the gate electrode.
Thirdly, a photoresist pattern having the same width of the gate electrode 30 is needed to form the gate electrode 30 as shown in FIG. 1A. If the line width of the gate electrode 30 is finely reduced, a margin for photolithography becomes short. Therefore, to form the gate having the fine line width, precision of equipment for photomasks needs to be enhanced. This can increase product costs.